The present invention relates to techniques for enhancing characteristics of semiconductor integrated circuit devices, and more particularly to techniques for low power consumption thereon.
Recent years have seen an increasing demand for low power consumption in semiconductor integrated circuit devices, typified by system LSI devices used for mobile apparatus or the like. In the art of low power consumption, there are known a power cutoff circuit technique and a DVFS (Dynamic Voltage Frequency Scaling) technique, for example.
In the power cutoff circuit technique, a semiconductor integrated circuit device is divided into a plurality of internal circuit blocks, and an inactive circuit block is powered off to suppress a leak current that would otherwise cause a significant amount of power consumption.
In the DVFS technique, an operating frequency and voltage to be applied to a circuit block such as a processor is dynamically varied in response to requirement for current performance. In cases where a plurality of circuit blocks use different power supply voltages, it is required to provide a level shifter (level shift circuit) for varying voltage levels of signals to be sent and received between core regions.